This invention relates to a serial input interface circuit which may be manufactured as a one-chip integrated circuit for use typically in a microcomputer.
In the manner which will later be described in greater detail, a serial input interface circuit is connected to a data bus and is supplied with input serial data to transfer the input serial data of a predetermined transfer bit length to the data bus as parallel data. The serial input interface circuit is put in operation of transferring the parallel data to the data bus by a handshake operation, namely, by cooperation in a handshake fashion or manner, of a serial input response or acknowledgement signal which is produced for supply to the serial input interface circuit by an external circuit in correspondence to a serial input request signal produced by the serial input interface circuit.
On carrying out transfer processing of the parallel data to the data bus, the input serial data are subjected to input processing by the handshake operation of the serial input request signal and the serial input response signal corresponding to the serial input request signal under consideration. During the input processing, the input serial data are supplied to and shifted in a shift register as a shifted signal. The shifted signal of the transfer bit length is stored in a parallel register as the parallel data. A parallel register empty flag is set to produce a parallel register empty signal of a high level to indicate that no parallel data is kept in the parallel register for transfer to the data bus. When the parallel register empty flag is reset, the parallel register empty signal is given a low level to indicate that the parallel regitser keeps a parallel data which should be transferred to the data bus.
The transfer processing is controlled by a parallel data transfer or parallel register read-out signal which is produced in compliance with a program used in dealing with the transfer processing. Inasmuch as the transfer processing is dealt with after the input processing, it is possible to understand that the program is for dealing with the transfer processing as well as the input processing.
It is often desired to suspend or interrupt the input processing by suspending production of the serial input request signal and consequently of the serial input response signal in correspondence to the serial input request signal in question. What should be noted in this connection is the fact that suspension or interruption of the input processing is objectionable while the parallel register keeps the parallel data for transfer to the data bus. In other words, the serial input interface circuit has a suspension capable state, only during which the input processing should be suspended.
It should furthermore be noted that the serial input request signal is produced by a hardware logic of the input interface circuit independently of the program. It has therefore been difficult in a conventional serial input interface circuit to suspend the input processing by a serial input suspension request signal produced as an interruption command in compliance with the program. This is because programming is difficult to produce the suspension request signal while the serial input interface circuit is put in the suspension capable state which is determined independently of the program.
It has moreover been impossible in a prior art serial input interface circuit to suspend the input processing merely while the parallel register empty flag is reset. This is because the serial input request signal is produced independently of the program when the parallel register empty signal is given the high level and therefore because the parallel register empty signal of the low level can not define production of the serial input request signal.